There is a rather cheap mainboard ASUS K14PA-U12 for 9004 EPYCs [1]. Strange, but it is missing support for 9005 Turin. How can this be (except of 400W+ models)? What do you think, could there be some true hardware issue making it impossible to workaround it in BIOS and thus no chance for coreboot either?
> Strange, but it is missing support for 9005 Turin. How can this be (except of 400W+ models)?
I'm not a board design specialst, but it is not uncommon that boards get newer revisions to support next gen CPUs with compatible sockets. I suspect ASUS K14PA-U12 is Turin PCU eligible, but the vendor possibly chose not to support Turin CPUs on the board. If there was a new revision of the board, then it possibly could support new CPUs.
> What do you think, could there be some true hardware issue making it impossible to workaround it in BIOS and thus no chance for coreboot either?
May be hardware incompatibility, if there are some modifications required to the design to support both Genoa and Turin. On the BIOS/coreboot side, it is possible to support both Genoa and Turin, even with a single flash image (only if the flash size is at least 32MB). It is software that needs board porting and testing.
EDIT: ASUS K14PA-U12 has only 16MB flash, so it can run only one firmware type at a time. I.e. if you plug Genoa CPU, you have to flash Genoa compatible FW. If you plug Turin CPU, you would have to flash Turin compatible FW.
One thing that’s interesting with servers built with these cpus is that any M.2 drives tend to use the PCIe Gen 3 lanes. If there are two drives, one is likely x4 with the other x2. If you want fast boot drives it is important to pay attention to this.
That's true. The PCIe lanes on EPYC server CPUs are divided into the main Gen5 links on the SERDES (like I explained in the post) and the other lower speed lanes (Gen3/Gen4) come from the Bonus links. It is shown on the figures in the post. These Bonus links are often used for devices with lower bandwidth, like BMC. This is also true for Gigabyte MZ33-AR1, so the NVMe M.2 disk is connected to the Bonus links working at Gen3 speeds, despite the board manual says: 1 x M.2 @Gen4 (which must be a vendor's mistake).
As the Gigabyte MZ33-AR1 porting effort progresses, coreboot has to add definitions for I/O bus initialization, such as SATA, USB, and PCI Express. If you are curious how it is done on an AMD Turin-based system or want to educate yourself about modern server SATA, USB, and PCIe buses, this blog post is for you.
There is a rather cheap mainboard ASUS K14PA-U12 for 9004 EPYCs [1]. Strange, but it is missing support for 9005 Turin. How can this be (except of 400W+ models)? What do you think, could there be some true hardware issue making it impossible to workaround it in BIOS and thus no chance for coreboot either?
[1] https://servers.asus.com/products/servers/server-motherboard...
> Strange, but it is missing support for 9005 Turin. How can this be (except of 400W+ models)?
I'm not a board design specialst, but it is not uncommon that boards get newer revisions to support next gen CPUs with compatible sockets. I suspect ASUS K14PA-U12 is Turin PCU eligible, but the vendor possibly chose not to support Turin CPUs on the board. If there was a new revision of the board, then it possibly could support new CPUs.
> What do you think, could there be some true hardware issue making it impossible to workaround it in BIOS and thus no chance for coreboot either?
May be hardware incompatibility, if there are some modifications required to the design to support both Genoa and Turin. On the BIOS/coreboot side, it is possible to support both Genoa and Turin, even with a single flash image (only if the flash size is at least 32MB). It is software that needs board porting and testing.
EDIT: ASUS K14PA-U12 has only 16MB flash, so it can run only one firmware type at a time. I.e. if you plug Genoa CPU, you have to flash Genoa compatible FW. If you plug Turin CPU, you would have to flash Turin compatible FW.
One thing that’s interesting with servers built with these cpus is that any M.2 drives tend to use the PCIe Gen 3 lanes. If there are two drives, one is likely x4 with the other x2. If you want fast boot drives it is important to pay attention to this.
That's true. The PCIe lanes on EPYC server CPUs are divided into the main Gen5 links on the SERDES (like I explained in the post) and the other lower speed lanes (Gen3/Gen4) come from the Bonus links. It is shown on the figures in the post. These Bonus links are often used for devices with lower bandwidth, like BMC. This is also true for Gigabyte MZ33-AR1, so the NVMe M.2 disk is connected to the Bonus links working at Gen3 speeds, despite the board manual says: 1 x M.2 @Gen4 (which must be a vendor's mistake).
As the Gigabyte MZ33-AR1 porting effort progresses, coreboot has to add definitions for I/O bus initialization, such as SATA, USB, and PCI Express. If you are curious how it is done on an AMD Turin-based system or want to educate yourself about modern server SATA, USB, and PCIe buses, this blog post is for you.