And if you are curious about the modern radiation hardened CPUs then the current state of the art ones are the MOOG BRE440 [0] and the BAE RAD5500 [1], 5545 [2] being the highest performance multi core one.
Even more interesting that they both use the IBM POWER architecture!
There have been a number of rad-hard SPARC chips from different vendors tthat have flown along the way, and I know Frontgrade/Gaisler currently sells a SPARC v8 version, which isn't that far behind the 'state of the art' as the e5500 based PPCs from BEA (at least as far as state of the art in space rated, rad-hard processors goes...it's a conservative market). Quite a few rad-hard ARMs out there farther down the performance curve.
Frontgrade also advertises a rad-hard RISC-V, as does Microchip (a PIC64 variant), that I know nothing about, but seems like an inevitable next step. Seems like you could grab some Xilinx rad-hard FPGA and bobs your uncle.
"The Beginning - In July of 1951, Bill Moog, Art Moog, and Lou Geyer pooled $3,000 and opened Moog Valve. They had limited resources..."
vs
"The Moog synthesizer (/moʊɡ/ MOHG) is a modular synthesizer invented by the American engineer Robert Moog in 1964. Moog's company, R. A. Moog Co., produced numerous..."
Very interesting! Definitely some jargon I’ve not come across before.
“The chips were made on a n-on-n+ epitaxial substrate to provide latchup control, extensive guard rings around transistors were used and hardened oxides”
This is standard semiconductor manufacturing jargon.
"Substrate" here refers to the silicon wafer on which the integrated circuits are made, which at the end of the manufacturing process is cut into individual chips, which are then packaged as CPUs in this case.
An epitaxial wafer is a wafer on which epitaxial growth has been done before the rest of the manufacturing process. The wafers are cut from a huge crystal that has been grown from molten silicon. Initially they have a uniform concentration of doping impurities throughout their volume.
Epitaxial growth means that an extra layer of silicon is grown on the wafer and the growth is done in such a manner that all the layer is a single crystal and its lattice continues the crystal of the wafer, without interface defects.
The purpose is to have a different concentration of impurities in the extra layer, compared with the base wafer. N-on-n+ means that the initial wafer contained N-doping impurities, e.g. antimony, in a very high concentration (+), so that its electrical resistance would be minimum, while the "n" epitaxial layer also contains an N-doping impurity, e.g. phosphorus, but in a much lower concentration, so that it has a high electrical resistivity.
Both the fabrication of silicon wafers and the epitaxial growth are typically done by other companies than those that make integrated circuits, so the IC maker, or a silicon foundry like TSMC, buys epitaxial wafers according to a certain specification and they use them as the starting material in their manufacturing process.
"Latchup control" is a term specific to CMOS integrated circuits. In CMOS there exists a parasitic thyristor (a.k.a. SCR) composed of 2 parasitic bipolar transistors. If the parasitic thyristor turns on, it applies a short-circuit on the power supply, causing a huge electrical current spike, which normally destroys the integrated circuit, perhaps also other things if the power supply is not protected against short circuits.
In order to prevent the latchup of the parasitic thyristor, the structure is modified in various ways to reduce the gain of the parasitic transistors. If the gain is low enough, the thyristor cannot turn on.
Using a simple n substrate (which is cheaper) results in a high gain for the parasitic pnp bipolar transistor. Using an epitaxial n-on-n+ wafer reduces the gain of the pnp, lowering the probability of latchup.
Guard rings around transistors (which are made by diffusing certain doping impurities and then possibly also covering the diffused ring with a polysilicon or metal ring) have various purposes, typically related to preventing the electrical breakdown of the transistors at lower voltages than intended. This is especially important for radiation-hardened devices, because the most frequent effect of the passage of a ionizing particle through the semiconductor would be to generate mobile charge carriers that could cause the electrical breakdown of a transistor.
"Hardened oxide" is a more ambiguous term, but I assume that here it refers to high-quality oxide, i.e. which has a high value for the electrical field that can be sustained without electrical breakdown.
Interesting combination of 'remarkable' and 'wtf' that we fling nuclear weapons around with the computational equivalent of a couple of TRS-80s[1]. I can only imagine the sighs of relief from the devs when things like the MIL-STD-1750a and later rad-hard SPARC and PPC variants came along.
[1] yes...I know the TRS-80 had a z80, not an 8085. Close enough.
On the flip side, the fact that those processors were enough to steer spacecraft make me feel like there’s also a decent amount of remarkable wtf in how much compute we have now and how little we get out of each instruction on average compared to what people were doing with these z80 equivalents.
Even hypersonic weapons with precision terminal guidance use truly ancient CPUs. Physics limits of molecular materials places a very low upper bound on the amount of compute required.
The rate at which an object in the physical world can alter its trajectory is ultimately limited by the strength of molecular bonds in the material it is made from. Exceed that limit and the object will disintegrate. This upper bound is extremely slow from the perspective of a CPU, making it computationally trivial. A computer can react orders of magnitude faster than the quickest physical objects.
Bad typesetting just indicates poor editing, not slop IMHO.
I guessed after about a second of thought that this actually meant 10^6. If I had to guess how this happened, somebody just wrote their prose in Word with the 6 in superscript and cut and paste it into HTML which lost the formatting.
I think it's a shame if you consider the whole article (which I personally found very interesting) as slop because of 2 incorrectly formatted numbers that could easily result from a cut-and-paste error. It's clear the article hadn't been well proof read as there are a number of spelling mistakes too, but that doesn't make the content itself slop.
Like others have mentioned, 50k small CPUs like 8085 can be made in a single production batch (i.e. a small basket containing silicon wafers, which passes through all manufacturing steps), so a number like this is likely to be the minimum amount that can be produced.
The customer would order this minimum quantity, and most of it will probably be kept as spares.
I assume the tooling and process are such that it’s a one-time thing, as in, this is the most of these chips that we could ever possibly need for all time. They’re not going to be able to spin up the same fab and build the same chips the same way again in the future whether that’s 5 or 50 years in the future. Given the long lifespans of military systems, it’s maybe not so crazy.
That number was probably shaped by minimum production-run requirements, alongside the need for software development units, along with other factors, like the use in Trident II and other quests we may not know about.
There isn't really a minimum production run for silicon chips, they do small test runs all the time to test new designs.
At least not from a practical perspective.
From an economic perspective, stopping after a single small run is just wasteful. The upfront design costs are so high, and the per wafer costs are so slow that you might as well make a lot extra. Maybe you can find a use for them, or sell them to someone else.
And if you are curious about the modern radiation hardened CPUs then the current state of the art ones are the MOOG BRE440 [0] and the BAE RAD5500 [1], 5545 [2] being the highest performance multi core one.
Even more interesting that they both use the IBM POWER architecture!
0, https://www.moog.com/products/avionics/spacecraft-avionics/b...
1, https://en.wikipedia.org/wiki/RAD5500
2, https://web.archive.org/web/20190226111129/https://www.baesy...
There have been a number of rad-hard SPARC chips from different vendors tthat have flown along the way, and I know Frontgrade/Gaisler currently sells a SPARC v8 version, which isn't that far behind the 'state of the art' as the e5500 based PPCs from BEA (at least as far as state of the art in space rated, rad-hard processors goes...it's a conservative market). Quite a few rad-hard ARMs out there farther down the performance curve.
Frontgrade also advertises a rad-hard RISC-V, as does Microchip (a PIC64 variant), that I know nothing about, but seems like an inevitable next step. Seems like you could grab some Xilinx rad-hard FPGA and bobs your uncle.
what scale of radiation do such hardened designs target?
1 Megarad (10 Kilogray)
In comparison radtherapy patients get 20 gray in 1-2 weeks so it's the 20/10000 = 0.02% of what these designs target
Wow, until you posted this I thought Moog was just a synthesizer company. And a bit of an odd one at that based on how I saw that synth presented.
Cousins. One made synths the other flight controls.
Very interesting! Definitely some jargon I’ve not come across before.
“The chips were made on a n-on-n+ epitaxial substrate to provide latchup control, extensive guard rings around transistors were used and hardened oxides”
This is standard semiconductor manufacturing jargon.
"Substrate" here refers to the silicon wafer on which the integrated circuits are made, which at the end of the manufacturing process is cut into individual chips, which are then packaged as CPUs in this case.
An epitaxial wafer is a wafer on which epitaxial growth has been done before the rest of the manufacturing process. The wafers are cut from a huge crystal that has been grown from molten silicon. Initially they have a uniform concentration of doping impurities throughout their volume.
Epitaxial growth means that an extra layer of silicon is grown on the wafer and the growth is done in such a manner that all the layer is a single crystal and its lattice continues the crystal of the wafer, without interface defects.
The purpose is to have a different concentration of impurities in the extra layer, compared with the base wafer. N-on-n+ means that the initial wafer contained N-doping impurities, e.g. antimony, in a very high concentration (+), so that its electrical resistance would be minimum, while the "n" epitaxial layer also contains an N-doping impurity, e.g. phosphorus, but in a much lower concentration, so that it has a high electrical resistivity.
Both the fabrication of silicon wafers and the epitaxial growth are typically done by other companies than those that make integrated circuits, so the IC maker, or a silicon foundry like TSMC, buys epitaxial wafers according to a certain specification and they use them as the starting material in their manufacturing process.
"Latchup control" is a term specific to CMOS integrated circuits. In CMOS there exists a parasitic thyristor (a.k.a. SCR) composed of 2 parasitic bipolar transistors. If the parasitic thyristor turns on, it applies a short-circuit on the power supply, causing a huge electrical current spike, which normally destroys the integrated circuit, perhaps also other things if the power supply is not protected against short circuits.
In order to prevent the latchup of the parasitic thyristor, the structure is modified in various ways to reduce the gain of the parasitic transistors. If the gain is low enough, the thyristor cannot turn on.
Using a simple n substrate (which is cheaper) results in a high gain for the parasitic pnp bipolar transistor. Using an epitaxial n-on-n+ wafer reduces the gain of the pnp, lowering the probability of latchup.
Guard rings around transistors (which are made by diffusing certain doping impurities and then possibly also covering the diffused ring with a polysilicon or metal ring) have various purposes, typically related to preventing the electrical breakdown of the transistors at lower voltages than intended. This is especially important for radiation-hardened devices, because the most frequent effect of the passage of a ionizing particle through the semiconductor would be to generate mobile charge carriers that could cause the electrical breakdown of a transistor.
"Hardened oxide" is a more ambiguous term, but I assume that here it refers to high-quality oxide, i.e. which has a high value for the electrical field that can be sustained without electrical breakdown.
Interesting combination of 'remarkable' and 'wtf' that we fling nuclear weapons around with the computational equivalent of a couple of TRS-80s[1]. I can only imagine the sighs of relief from the devs when things like the MIL-STD-1750a and later rad-hard SPARC and PPC variants came along.
[1] yes...I know the TRS-80 had a z80, not an 8085. Close enough.
On the flip side, the fact that those processors were enough to steer spacecraft make me feel like there’s also a decent amount of remarkable wtf in how much compute we have now and how little we get out of each instruction on average compared to what people were doing with these z80 equivalents.
Even hypersonic weapons with precision terminal guidance use truly ancient CPUs. Physics limits of molecular materials places a very low upper bound on the amount of compute required.
The rate at which an object in the physical world can alter its trajectory is ultimately limited by the strength of molecular bonds in the material it is made from. Exceed that limit and the object will disintegrate. This upper bound is extremely slow from the perspective of a CPU, making it computationally trivial. A computer can react orders of magnitude faster than the quickest physical objects.
> I can only imagine the sighs of relief from the devs when things like the MIL-STD-1750a and later rad-hard SPARC and PPC variants came along.
What, so that they can debug in Chrome and put the fusing and inertial navigation processes in isolated web views?
You don't need much calculation power to manage a 30-min ballistic trajectory.
The inertial navigation system is the very crazy part, along with the nuclear fusion warhead design itself.
https://youtu.be/AazmxNs5kmE?is=2LE2q3rBSWDyTs7j
I was under the impression that the Trident II could do terminal phase maneuvering, so not a straight ballistic trajectory, but fair enough.
It controls the fusing, not positioning.
https://thebulletin.org/2017/03/how-us-nuclear-force-moderni...
This is slop, but perhaps the old-fashioned kind.
> An 8085 processor that could handle 1×106 rads of radiation with only a 25% reduction in performance, and 3×106 rads with a 40% drop.
Hmm, from where did they copy-paste this mangled scientific notation?
Ah here we are, pg. 37 (46 in PDF file): https://apps.dtic.mil/sti/tr/pdf/ADA063902.pdf
Excellent find. And yes, obviously this is slop. 106 rad is exactly nothing for nuclear usage.
Bad typesetting just indicates poor editing, not slop IMHO.
I guessed after about a second of thought that this actually meant 10^6. If I had to guess how this happened, somebody just wrote their prose in Word with the 6 in superscript and cut and paste it into HTML which lost the formatting.
I think it's a shame if you consider the whole article (which I personally found very interesting) as slop because of 2 incorrectly formatted numbers that could easily result from a cut-and-paste error. It's clear the article hadn't been well proof read as there are a number of spelling mistakes too, but that doesn't make the content itself slop.
Yeah, but 318 should probably suffice.
> Galileo space probe [..] How many IC’s were needed? Over 50,000 for the probe itself, backups, testing chips etc.
I seriously doubt you need to fabricate 50k CPUs for a single space probe, including backups, testing chips, etc.
Like others have mentioned, 50k small CPUs like 8085 can be made in a single production batch (i.e. a small basket containing silicon wafers, which passes through all manufacturing steps), so a number like this is likely to be the minimum amount that can be produced.
The customer would order this minimum quantity, and most of it will probably be kept as spares.
I assume the tooling and process are such that it’s a one-time thing, as in, this is the most of these chips that we could ever possibly need for all time. They’re not going to be able to spin up the same fab and build the same chips the same way again in the future whether that’s 5 or 50 years in the future. Given the long lifespans of military systems, it’s maybe not so crazy.
That number was probably shaped by minimum production-run requirements, alongside the need for software development units, along with other factors, like the use in Trident II and other quests we may not know about.
There isn't really a minimum production run for silicon chips, they do small test runs all the time to test new designs.
At least not from a practical perspective.
From an economic perspective, stopping after a single small run is just wasteful. The upfront design costs are so high, and the per wafer costs are so slow that you might as well make a lot extra. Maybe you can find a use for them, or sell them to someone else.
> other quests we may not know about.
Back then an interface between terrestrial computer systems and a Zeta Reticulan spacecraft required a small supercomputer on our side.
I also am curious about that statement. Seems something got mixed up between the quantity of the full run and the quantity for the probe.