I've been looking forward to RISC-V for a long time and seeing as the semiconductors industry has typically been heavily gated, it came as a surprise that nobody had yet tried adapting a build environment to start your own CPU company with Claude if you want it. So I've been reading a lot about SystemVerilog, the RISC-V specs covering everything about cpu design, how it works through controllers to get to the boards, and I wrote a repo with all agentic features, build-platform, etc. licensed as MIT for anyone interested in the subject.
Essentially, I had Claude analyze the specs and build up summarized chapter-based sections on status with CV6, towards modelling the development and making Claude write through my instructions how it needs to navigate everything as it develops in SiliconVerilog or even using SKiDL to create a custom board. It's still passing all the CV6 tests but the agentic boilerplace is pretty much in place and ready to tinker with processor development!
I've been looking forward to RISC-V for a long time and seeing as the semiconductors industry has typically been heavily gated, it came as a surprise that nobody had yet tried adapting a build environment to start your own CPU company with Claude if you want it. So I've been reading a lot about SystemVerilog, the RISC-V specs covering everything about cpu design, how it works through controllers to get to the boards, and I wrote a repo with all agentic features, build-platform, etc. licensed as MIT for anyone interested in the subject.
Essentially, I had Claude analyze the specs and build up summarized chapter-based sections on status with CV6, towards modelling the development and making Claude write through my instructions how it needs to navigate everything as it develops in SiliconVerilog or even using SKiDL to create a custom board. It's still passing all the CV6 tests but the agentic boilerplace is pretty much in place and ready to tinker with processor development!
https://cimons.com/article/developing-a-risc-v-processor-soc...