This is a "build it and they will come" project.
It's not a "we put the inner loop of ML entirely in hardware" project. That would make more sense technically. You could cram a lot of little independent neural net inference units on one chip. But if it was pitched that way, the questions would be "Why isn't NVidia doing this", and "After you do it, what keeps NVidia from doing it". There are lots of people pitching "AI chips", with modest success.
The history of general-purpose massively parallel machines isn't good. From the Illiac IV to the Playstation 3, there's been dud after dud in this space. You can build them, but the users don't come. This sort of architecture is great if you have some specific problem that parallelizes, such as finite-element analysis or neural networks.
(I've used an NCube, and I kind of liked the Transputer concept. But both were dead ends.)
"Instead of starting from a sequential design, we’re building our processor to have thousands of cores operating in parallel. This requires moving beyond the notion of shared mutable memory and linear instruction sequences. To make this possible, we’re working in tandem on the open-source language Vine, which has been designed from the beginning to target a new wave of parallel-first architectures."
I wish them well but from their Vine language docs:
"For example, a < b < c is equivalent to (a < b) & (b < c)"
So how do you parallelize that? You can run the first part on 2 cores in parallel, but there is still a single check, a single cache, a single CPU for this to go through to complete the operation, right?
With that context, this example is a minimal example for explaining `and` short circuits and `&` does not. I.e. the `a < b < c is equivalent to (a < b) & (b < c)` is just explaining the logical behavior (with even more verbose equivilant logic after), not showing off how this particular example will parallelize better as part of introing the conditional operators behavior.
This exists to allow you to control whether parallel computation should happen or if it should resolve the first condition before wasting parallel compute to resolve the nth condition(s). E.g. imagine something like `isEven(x) & len(factor(x) > 2` vs `isEven(x) and len(factor(x) > 2` (but the functions can be a lot more complicated). Maybe you want to tell the compiler to short circuit and save average compute at the cost of total latency, maybe you want to tell the compiler to schedule both in parallel and get the better max latency at the cost of running more compute. Especially if you do vast numbers of such things as a workload vs just a few as a dependency.
I haven't read through the rest of everything to see if they have anything interesting compared to other parallel computation solutions, I just know this example isn't supposed to help answer that one way or the other.
I always wonder where will x86 be in 10 or 20 years time. As data paths widen for SIMD, how many can they possibly cram , such as more generations of wider and wider groups of instruction with different opcodes and characteristics.
Do you remember the 1990s everlasting arguments about RISC vs CISC? There were so many arguments (online and magazines) saying that "soon" RISC would eat CISC. And yet, it never happened. I'll be dead before the demise of x86. More likely: The computing landscape will get more complex. Probably ARM will become a legitimate competitor to x86 outside of handheld computing, and RISC V will become a legitimate competitor to ARM for single board and handheld computing.
> CUDA is a huge reason NVidia is so big right now. Their GPUs are broadly similar to AMD. Their software libraries are better.
This was pre-2026 story. CUDA isn't a moat anymore.
Now it's mostly market dynamics: People always ship ad optimize things for Nvidia because it's the most widely used platform, and people buy it because it has the most software.
This is much less of a barrier than it used to be though. Buggy AMD GPU drivers remain a problem though.
> it is the compiler to use it that is the hard hard part
We're in a wildly different world from the one Itanium got to live in and compilers are something with a super tight automated verification loop that can make LLMs thrive. Add that plus cheap formal verification and I think this concern goes away almost completely.
"Instead of starting from a sequential design, we’re building our processor to have thousands of cores operating in parallel. This requires moving beyond the notion of shared mutable memory and linear instruction sequences. To make this possible, we’re working in tandem on the open-source language Vine, which has been designed from the beginning to target a new wave of parallel-first architectures."
Reminds me of the Transputer and Occam. Each transputer had 4 comm links to form a flexible network of processors and Occam supported parallelism. Also one of the first languages to use indentation for block structures.
I'm quite interested to see how this evolves. But part of me is still being sad, because hardware is rarely the bottleneck these days - as opposed to software.
Have you seen the new CPU architecture? It's on Mill. It's literally on Transputer. It's on Rock with Sun. It's literally on AMULET. You can probably find it on Itanium. Dude it's on Tesla. It's a CDC STAR original. It's on E1. You can program it on E1. You can go to E1 and program it. Get onto E1 right now. Go to E1. Dive into E1. You can E1 it. It's on E1. E1 has it for you. E1 has it for you.
In all seriousness congratulations on finding $30 million to launder and lose immediately. Hope your Porsche runs good.
Really would like to understand how the mill got going and how anyone can see it progressing at this point. I know folks are working on it on the side but it's just bleh now.
> Sources say that the company is already discussing a fast follow-up raise that would potentially value the firm at more than $1 billion. Neither round has previously been reported. Benchmark declined to comment.
This is a "build it and they will come" project. It's not a "we put the inner loop of ML entirely in hardware" project. That would make more sense technically. You could cram a lot of little independent neural net inference units on one chip. But if it was pitched that way, the questions would be "Why isn't NVidia doing this", and "After you do it, what keeps NVidia from doing it". There are lots of people pitching "AI chips", with modest success.
The history of general-purpose massively parallel machines isn't good. From the Illiac IV to the Playstation 3, there's been dud after dud in this space. You can build them, but the users don't come. This sort of architecture is great if you have some specific problem that parallelizes, such as finite-element analysis or neural networks.
(I've used an NCube, and I kind of liked the Transputer concept. But both were dead ends.)
This is my first time hearing about Vine - https://vine.dev/ I have to say the landing page is terrible, at least show an example of the language.
Hmm. The story over at https://millcomputing.com/ always looked compelling.
Pitchbook shows it as "Out of Business" since 2019.
They spent way too long procrastinating, with zero silicon after decades of work.
For comparison, RISC-V started years later and had a tapeout within a year and working silicon available as a commercial product in seven years.
2003: Mill computing started
2010: RISC-V project started
2011: RISC-V first tapeout
2017: RISC-V production chips available in the market
2019: Mill computing dead?
From the URL:
"Instead of starting from a sequential design, we’re building our processor to have thousands of cores operating in parallel. This requires moving beyond the notion of shared mutable memory and linear instruction sequences. To make this possible, we’re working in tandem on the open-source language Vine, which has been designed from the beginning to target a new wave of parallel-first architectures."
I wish them well but from their Vine language docs:
"For example, a < b < c is equivalent to (a < b) & (b < c)"
So how do you parallelize that? You can run the first part on 2 cores in parallel, but there is still a single check, a single cache, a single CPU for this to go through to complete the operation, right?
It took me a second to find you were referencing section 2.8 https://vine.dev/docs/features/conditions
With that context, this example is a minimal example for explaining `and` short circuits and `&` does not. I.e. the `a < b < c is equivalent to (a < b) & (b < c)` is just explaining the logical behavior (with even more verbose equivilant logic after), not showing off how this particular example will parallelize better as part of introing the conditional operators behavior.
This exists to allow you to control whether parallel computation should happen or if it should resolve the first condition before wasting parallel compute to resolve the nth condition(s). E.g. imagine something like `isEven(x) & len(factor(x) > 2` vs `isEven(x) and len(factor(x) > 2` (but the functions can be a lot more complicated). Maybe you want to tell the compiler to short circuit and save average compute at the cost of total latency, maybe you want to tell the compiler to schedule both in parallel and get the better max latency at the cost of running more compute. Especially if you do vast numbers of such things as a workload vs just a few as a dependency.
I haven't read through the rest of everything to see if they have anything interesting compared to other parallel computation solutions, I just know this example isn't supposed to help answer that one way or the other.
I think thats a poor example (either that, or less charitably, they're scamming investors).
They just described a common superscalar optimization thats been done since the 90s.
I always wonder where will x86 be in 10 or 20 years time. As data paths widen for SIMD, how many can they possibly cram , such as more generations of wider and wider groups of instruction with different opcodes and characteristics.
Do you remember the 1990s everlasting arguments about RISC vs CISC? There were so many arguments (online and magazines) saying that "soon" RISC would eat CISC. And yet, it never happened. I'll be dead before the demise of x86. More likely: The computing landscape will get more complex. Probably ARM will become a legitimate competitor to x86 outside of handheld computing, and RISC V will become a legitimate competitor to ARM for single board and handheld computing.
> Probably ARM will become a legitimate competitor to x86 outside of handheld computing
Err..
Are Apple Silicon and Nvidia Vera and Amazon Graviton are considered illegitimate or non-competitors for some reason?
Isn't this basically a GPU?
Not necessarily, there are other kinds of accelerator designs like dataflow architectures or systolic arrays.
> This requires moving beyond the notion of shared mutable memory and linear instruction sequences.
Sure looks like it.
But they are ignoring the basic lesson of "new" CPU designs from Transputer to i432 to Itanium to Transmeta.
A new CPU design is easy, it is the compiler to use it that is the hard hard part.
Looked at another way, CUDA is a huge reason NVidia is so big right now. Their GPUs are broadly similar to AMD. Their software libraries are better.
But good luck to them, perhaps they have some great new idea. We need one.
> CUDA is a huge reason NVidia is so big right now. Their GPUs are broadly similar to AMD. Their software libraries are better.
This was pre-2026 story. CUDA isn't a moat anymore.
Now it's mostly market dynamics: People always ship ad optimize things for Nvidia because it's the most widely used platform, and people buy it because it has the most software.
This is much less of a barrier than it used to be though. Buggy AMD GPU drivers remain a problem though.
> it is the compiler to use it that is the hard hard part
We're in a wildly different world from the one Itanium got to live in and compilers are something with a super tight automated verification loop that can make LLMs thrive. Add that plus cheap formal verification and I think this concern goes away almost completely.
Yep, and they're probably simulating/emulating their CPU design on GPUs already.
FTA:
"Instead of starting from a sequential design, we’re building our processor to have thousands of cores operating in parallel. This requires moving beyond the notion of shared mutable memory and linear instruction sequences. To make this possible, we’re working in tandem on the open-source language Vine, which has been designed from the beginning to target a new wave of parallel-first architectures."
Reminds me of the Transputer and Occam. Each transputer had 4 comm links to form a flexible network of processors and Occam supported parallelism. Also one of the first languages to use indentation for block structures.
For a long time I missed their folding editor.
How will this be better than RISC V?
Who do you expect to answer? It's a tiny future product announcement, it neither exists, nor is it a Show HN from someone involved
a man can dream
I'm quite interested to see how this evolves. But part of me is still being sad, because hardware is rarely the bottleneck these days - as opposed to software.
Have you seen the new CPU architecture? It's on Mill. It's literally on Transputer. It's on Rock with Sun. It's literally on AMULET. You can probably find it on Itanium. Dude it's on Tesla. It's a CDC STAR original. It's on E1. You can program it on E1. You can go to E1 and program it. Get onto E1 right now. Go to E1. Dive into E1. You can E1 it. It's on E1. E1 has it for you. E1 has it for you.
In all seriousness congratulations on finding $30 million to launder and lose immediately. Hope your Porsche runs good.
Really would like to understand how the mill got going and how anyone can see it progressing at this point. I know folks are working on it on the side but it's just bleh now.
it’s the Transputer again, or the Emotion Engine again, depending on how old you are
> Sources say that the company is already discussing a fast follow-up raise that would potentially value the firm at more than $1 billion. Neither round has previously been reported. Benchmark declined to comment.
https://www.newcomer.co/p/scoop-benchmark-backs-early-stage
VC is such a meme lmao. What’s next, Sam gonna acquire the company? No product needed!
Maybe now the cpu arena is a patent graveyard instead of a patent minefield, some fresh developments can appear.
let's re-do the OS too. we only need about 10 syscalls. authorization is totally backwards (look how android runs a user per process).
Was about time we had another Transmeta.
Bet you they will turn into yet another ML accelerator company within the year.
TL;DR: it's basically Niagara/GreenArrays/etc again.
Not sure why this one will succeed where its forebears didn't.