This is my post. Basically, I needed P2P between four R9700s for tensor parallel serving, which means a 32 GB BAR on each card. With all six GPUs in, the BIOS couldn't map them, and Linux sized the switch's window too small, so only two cards got their BARs. The module in the post works around that. With P2P off, prefill was about half as fast.
Odd. I'm using 7 GPUs (8 if you include the onboard AST2500) and haven't had this issue, but these are directly connected to the mainboard
I did disable CSM which used base memory resources needed by REBAR, but aside from that I've 6x Tesla P4s, 1x 750TI, and the AST2500 all happily working together.
My board is a Cloud Star C612 (6x DDR4 variant), 2 PCIE ports bifurcated (so 4 GPUs in total, the others sit on dedicated ports), with a Xeon E5 2696v3 and TBU.
The gpu_unlock is a bit hacky (but I have many GPUs that the unlock won't work on and that will cause issues), and there are two BIOS settings that matter: above 4GB decode enabled and resizeable bar enabled. That's it.
These kind of things should be fun to test in Coreboot. When Dasharo was released for the MSI PRO Z690-A DDR4 more than four years ago, I had issues with two Radeon 5600XT installed that was fixed after developer tuned some MMIO related parameters: https://github.com/Dasharo/dasharo-issues/issues/245
How many PCIe Switches you could chain and how many cards with absurd MMIO requeriments you can get working would be an interesing experiment.
In the last decade or so I have seen plenty of Firmware MMIO related issues. I remember certain SR-IOV supporting NICs (Usually Intel ones like i350 and other enterprise parts) not being able to reserve enough MMIO to create all the supported SR-IOV Virtual Functions in consumer Motherboards, in many cases you could get SR-IOV working but were limited to create like 4 VFs even if hardware supported 16 because that is what you could fit. This was essentially all a Firmware issue, not Hardware, but few people has the required skills to do any BIOS modding to fix rather convoluted things like MMIO allocation. Basically, you're trying to workaround Firmware issues elsewhere.
The bottleneck with AI and hardware is really pushing things.
Even with six capable GPUs that have plenty of VRAM with enough PCIe bandwidth, you then discover that memory address allocation is preventing the hardware from doing what it's physically capable of.
Most CPUs can address 48 bits of physical memory (hundreds of terabytes), why is that even a problem ? Is it just some hardware limitation somewhere else or badly written firmware ?
There was never a concerted effort in the PC ecosystem to force all peripherals and firmware to drop 32-bit compatibility. At some point after a decade or two of x86-64 CPUs, we should have started making GPUs that simply exposed all of their VRAM to be mapped by the host by default, instead of retaining compatibility hacks like only mapping 256MB by default. Resizable BARs should have happened at least a decade earlier, and should have been phased out by now in favor of just always mapping all the VRAM.
Yeah, it's the firmware. It's an AM4 board, and the BIOS only gives PCI devices the space from the top of RAM up to 512 GB. Each 32 GB BAR has to start on a 32 GB boundary, and its small doorbell BAR spills into the next slot, so each card needs 64 GB. Six won't fit. So I turn Resizable BAR off in the BIOS and resize the four R9700s from Linux, where I hit the kernel bug.
The problem is that with P2P every card will map every other card into its address space. So you're not mapping 128G but likely 512! It depends a bit on what software you use, some software is smart about this and uses a smaller sliding window if it can't use all of it at once and some software is really rigid.
It feels ridiculous that a person has to go to these kind of lengths to do what is in the end a trivial thing: assigning little pieces of a gigantic virtual address space to specific peripherals.
The only thing that's complex here is having to influence a bunch of hidden software through three layers of indirection. The software is all standing in the way of a person just writing some values to registers.
Another important benefit is that transfers between cards flow across the switch and bypass the CPU, that ain't nothing. At least for the AMD cards. Nvidia firmware refuses nach
This is my post. Basically, I needed P2P between four R9700s for tensor parallel serving, which means a 32 GB BAR on each card. With all six GPUs in, the BIOS couldn't map them, and Linux sized the switch's window too small, so only two cards got their BARs. The module in the post works around that. With P2P off, prefill was about half as fast.
Odd. I'm using 7 GPUs (8 if you include the onboard AST2500) and haven't had this issue, but these are directly connected to the mainboard
I did disable CSM which used base memory resources needed by REBAR, but aside from that I've 6x Tesla P4s, 1x 750TI, and the AST2500 all happily working together.
My board is a Cloud Star C612 (6x DDR4 variant), 2 PCIE ports bifurcated (so 4 GPUs in total, the others sit on dedicated ports), with a Xeon E5 2696v3 and TBU.
Interesting. This sort of thing is highly bios specific, I'm running 240G of VRAM on a single box using a very simple config:
GRUB_CMDLINE_LINUX_DEFAULT="pcie_aspm=off amd_iommu=on iommu=pt pci=realloc,firmware noapic nomodeset pci=nommconf gpu_unlock.targets=0000:66:00.0,0000:69:00.0,0000:6d:00.0,0000:6e:00.0"
The gpu_unlock is a bit hacky (but I have many GPUs that the unlock won't work on and that will cause issues), and there are two BIOS settings that matter: above 4GB decode enabled and resizeable bar enabled. That's it.
sidebar: Why don't your posts include pics of your rig?
Asking because I really want to see your kit.
I'll get a post together with some photos of the rat's nest soon. It's definitely not fancy. :-)
I think a lot of folks use open air aluminum extrusion frames that were once meant for mining.
You into liquid cooling?
because the llm who wrote and illustrated it doesn't have a camera
These kind of things should be fun to test in Coreboot. When Dasharo was released for the MSI PRO Z690-A DDR4 more than four years ago, I had issues with two Radeon 5600XT installed that was fixed after developer tuned some MMIO related parameters: https://github.com/Dasharo/dasharo-issues/issues/245 How many PCIe Switches you could chain and how many cards with absurd MMIO requeriments you can get working would be an interesing experiment.
In the last decade or so I have seen plenty of Firmware MMIO related issues. I remember certain SR-IOV supporting NICs (Usually Intel ones like i350 and other enterprise parts) not being able to reserve enough MMIO to create all the supported SR-IOV Virtual Functions in consumer Motherboards, in many cases you could get SR-IOV working but were limited to create like 4 VFs even if hardware supported 16 because that is what you could fit. This was essentially all a Firmware issue, not Hardware, but few people has the required skills to do any BIOS modding to fix rather convoluted things like MMIO allocation. Basically, you're trying to workaround Firmware issues elsewhere.
The bottleneck with AI and hardware is really pushing things.
Even with six capable GPUs that have plenty of VRAM with enough PCIe bandwidth, you then discover that memory address allocation is preventing the hardware from doing what it's physically capable of.
The word or acronym BAR is mentioned 34 times but never defined.
thanks, fixed
What are you running on this? I have a very similar set up to you, a skylake beast 32GiB of DDR4 goodness and a monster 8GB RX570.
All jokes aside I would love to know more about your set up and what you do with it and what speeds you get token wise.
Most CPUs can address 48 bits of physical memory (hundreds of terabytes), why is that even a problem ? Is it just some hardware limitation somewhere else or badly written firmware ?
There was never a concerted effort in the PC ecosystem to force all peripherals and firmware to drop 32-bit compatibility. At some point after a decade or two of x86-64 CPUs, we should have started making GPUs that simply exposed all of their VRAM to be mapped by the host by default, instead of retaining compatibility hacks like only mapping 256MB by default. Resizable BARs should have happened at least a decade earlier, and should have been phased out by now in favor of just always mapping all the VRAM.
Yeah, it's the firmware. It's an AM4 board, and the BIOS only gives PCI devices the space from the top of RAM up to 512 GB. Each 32 GB BAR has to start on a 32 GB boundary, and its small doorbell BAR spills into the next slot, so each card needs 64 GB. Six won't fit. So I turn Resizable BAR off in the BIOS and resize the four R9700s from Linux, where I hit the kernel bug.
The problem is that with P2P every card will map every other card into its address space. So you're not mapping 128G but likely 512! It depends a bit on what software you use, some software is smart about this and uses a smaller sliding window if it can't use all of it at once and some software is really rigid.
"640kB ought to be enough for everyone" moment.
I wonder if AI could RE the BIOS enough to fix that limit
It feels ridiculous that a person has to go to these kind of lengths to do what is in the end a trivial thing: assigning little pieces of a gigantic virtual address space to specific peripherals.
The only thing that's complex here is having to influence a bunch of hidden software through three layers of indirection. The software is all standing in the way of a person just writing some values to registers.
Feels nostalgic. Kind of like Linux in the 90s. :)
Another important benefit is that transfers between cards flow across the switch and bypass the CPU, that ain't nothing. At least for the AMD cards. Nvidia firmware refuses nach